The
most frequently asked question in the interview is regarding the timing of
flops. Generally the questions asked are based on calculation of minimum time
cycle (max. frequency), setup slack and hold slack.
Consider a D
–type edge-triggered, Flip Flop (FF). The time just before and just after the
clock edge, is the critical time, where the D input must not change.
Region just
before the clock is setup time (tsetup).
Region after
the clock edge is hold time (thold).
Every flip
flop has minimum required values for tsetup and thold.
The values of tsetup and thold vary strongly with
temperature, voltage and process.
What happens to Q if D input changes
within the tsetup and thold window?
- Q may follow D correctly.
- Q may follow D incorrectly.
- Q may assume a metastable state for an indeterminate time followed by a transition to logic 1 or logic 0.
For correct operation, D
inputs must be stable for tsetup prior to clock and stay stable for
a thold afterwards.
Minimum
Cycle Time:
Time taken by
data to travel from one flop to another flop. Path between
two flops is composed of :
- Clock to Q delay (tclk-q).
- Propogation delay through the combo logic. (tcombo).
- The required setup time (tsetup) of FF1.
tmin = tclk-q + tcombo + tsetup
fmax = 1/tmin
Setup Slack:
The setup time is a function of the clock period, combo delay
and the clk-to-output delay.
Actual tsetup = tclk – tclk-q
- tcombo
As said earlier, each flop has a minimum specified tsetup.
The difference between the actual setup time and the minimum
required setup time is known as setup slack.
Setup Slack = Actual tsetup – Reqd. tsetup
A positive slack is always desirable.
For maximum frequency, the setup slack is zero.
Hold Time:
Hold time is
the amount of time that FF0’s old data must persist at the D input of FF1, i.e.
D1 after the clock edge.
Actual hold
time = tclk-q + tcombo.
Each flop
has a minimum specified thold. The difference between the actual hold time and the minimum required hold time is known as hold slack.
Hold slack =
Actual hold time – Reqd. thold
For examples, please visit Setup and Hold time for flip flops - Part 2
For Verilog timing tasks related to setup and timing checks, please go through this link.
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