Clock Skew

Clock skew

The operation of most digital circuit systems, such as computer systems, is synchronized by a "clock" that dictates the sequence and pacing of the devices on the circuit. Ideally, the input to each element has reached its final value before the next clock movement occurs so that the behaviour of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.

In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. Clock skew can be positive or negative. If the clock signals are in complete synchronicity, then the clock skew observed at the registers is zero.

Reasons for clock skew:

This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

Two types of skews are defined: Local skew and Global skew.

Local skew

Local skew is the difference in the arrival of clock signal at the clock pin of related flops.

Global skew

Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This is also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

Why clock skew is a problem?

Two types of violation can be caused by clock skew. One problem is caused when the clock travels slower than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through.

Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, because the new data was not set up and stable before the next clock tick arrived. 

A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Positive Skew

When the source flop is clocked first than the destination flop, the clock skew is called as positive skew.

From the below waveform, we can see that the hold slack reduces, when there is a positive skew. Hence, we can infer that the positive skew increases the chances of hold violation.

Negative Skew
When the destination is clocked before the source, the clock skew is called as negative skew.

From the waveform below, we can see that the setup slack decreases in case of negative skew. So, the negative skew increases the chances of setup violation.

Uncertainty
Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.

ALSO READ : Clock Jiiter

Setup and Hold time for flip flops - Part 2

This post is in continuation to our previous post on Setup and Hold time for flip flops.

Q.1) Calculate the setup slack for the below example :

         t_clk-q = 300ps ; t_setup = 100ps ; t_combo = 400ps ; t_clk = 1000ps

Answer) 

                From the above waveform, we can derive the following equation :

                  t_clk = t_clk-q + t_combo + t_setup + setup-slack

                  So, setup-slack = t_clk – t_clk-q – t_combo  - t_setup

                  Hence, setup-slack = 1000 – 300 – 400 -200

                                          = 100ps

Q.2) Calculate the minimum clock cycle time, for the above example.

Answer) For the minimum clock cycle time, the setup slack is zero.
              Hence,  t_clk = t_clk-q + t_combo + t_setup + setup-slack becomes,
                      t_{clk (min.)} = t_clk-q + t_combo + t_setup
                      t_{clk (min.)} = 300 + 400 + 200
                      t_{clk (min.)} = 900ps 

Q.3) Calculate the hold slack for the above example. (t_hold = 100ps)

Answer) 

                From the above waveform, the equation for the hold slack comes as :
                                    hold-slack = t_clk-q + t_combo – t_hold

                             hold-slack = 300 + 400 – 100

                                          = 600ps

Q.4) Explain the  worst case hold time scenario.

Answer) The following equation is an analysis of worst case hold time scenarios. In this case, two FFs are directly connected to each other, i.e. there is no combo delay.

As depicted in the diagram, output Q0 of FF0 is directly connected to D1 of FF1.

Since, for worst case :  t_combo = 0
So the equation becomes,

                                    hold-slack = t_clk-q – t_hold

Since, hold-slack > 0 , as to avoid hold violation.

                                    t_clk-q – t_hold > 0

                                    t_clk-q > t_hold

                             hold-slack = t_clk-q + t_combo – t_hold       

For Verilog timing tasks related to setup and timing checks,  please go through this link.

Setup and Hold time for flip flops

The most frequently asked question in the interview is regarding the timing of flops. Generally the questions asked are based on calculation of minimum time cycle (max. frequency), setup slack and hold slack. 

Consider a D –type edge-triggered, Flip Flop (FF). The time just before and just after the clock edge, is the critical time, where the D input must not change.

Region just before the clock is setup time (t_setup).

Region after the clock edge is hold time (t_hold).

Every flip flop has minimum required values for t_setup and t_hold. The values of t_setup and t_hold vary strongly with temperature, voltage and process.

What happens to Q if D input changes within the t_setup and t_hold window?

• Q may follow D correctly.
• Q may follow D incorrectly.
• Q may assume a metastable state for an indeterminate time followed by a transition to logic 1 or logic 0.

For correct operation, D inputs must be stable for t_setup prior to clock and stay stable for a t_hold afterwards.

Minimum Cycle Time:

Time taken by data to travel from one flop to another flop. Path between two flops is composed of :

• Clock to Q delay (t_clk-q).
• Propogation delay through the combo logic. (tcombo).
• The required setup time (t_setup) of FF1.

  

        t_min  = t_clk-q + t_combo + t_setup 

f_max = 1/t_min

Setup Slack:

The setup time is a function of the clock period, combo delay and the clk-to-output delay.

Actual t_setup = t_clk – t_clk-q - t_combo

As said earlier, each flop has a minimum specified t_setup.

The difference between the actual setup time and the minimum required setup time is known as setup slack.

Setup Slack = Actual t_setup – Reqd. t_setup

A positive slack is always desirable. 

For maximum frequency, the setup slack is zero.

Hold Time:

Hold time is the amount of time that FF0’s old data must persist at the D input of FF1, i.e. D1 after the clock edge.

Actual hold time = t_clk-q + t_combo.

Each flop has a minimum specified t_hold. The difference between the actual hold time and the minimum required hold time is known as hold slack.

Hold slack = Actual hold time – Reqd. t_hold 

For examples, please visit Setup and Hold time for flip flops - Part 2
For Verilog timing tasks related to setup and timing checks,  please go through this link.