Clock Jitter

Jitter

Jitter is the short-term variations of a signal with respect to its ideal position in time. Jitter is the variation of the clock period from edge to edge. 

Clock jitter refers to temporal variation of clock period at a given point-that is, the clock period can reduce or expand on cycle by cycle basis. it is strictly a temporal uncertainty measure and is often specified at a given point on the chip. 

From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. Jitter can also be generated from PLL known as PLL jitter. Possible jitter values should be considered for proper PLL design. 

Jitter can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform

Sources of Jitter Common sources of jitter include:

• Internal circuitry of the phase-locked loop (PLL)
• Random thermal noise from a crystal
• Other resonating devices
• Random mechanical noise from crystal vibration
• Signal transmitters
• Traces and cables
• Connectors
• Receivers

Impact of Jitter on sequential system

Jitter directly impacts the performance of a sequential system. Ideally, the clock period starts at edge 2 and ends at edge 5 and with a nominal clock period of TCLK. However as a result of jitter, the worst case scenario happens when the leading edge of the current clock period is delayed (edge 3), and the leading edge of the next clock period occurs early (edge 4). As a result, the total time available to complete the operation is reduced by twice t_{jitter in the worst case.}