Q.1) What do you understand by UPF?
Answer) Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.
UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process — RTL (register transfer level) or earlier.
UPF provides a consistent format to specify power-aware design information that cannot be specified in HDL code or when it is undesirable to directly specify within the HDL logic, as doing so would tie the logic specification directly to a constrained power implementation.
Q.2) Explain different approaches of state retention.
Answer) Given a power switching fabric and an isolation strategy, it is possible to power gate a block of logic, but unless a retention strategy is employed, all state information is lost when the block is powered down. To resume its operation on power up, the block must either have its state restored from an external source or build up its state from the reset condition. In either case, the time and power required can be significant. The following three approaches can be used.
- A software approach based on reading and writing registers.
- A scan-based approach based on the re-use of scan chains to store state off chip.
- A register-based approach that uses retention registers.
Q.3) Explain glitching power dissipation and ways to minimize it.
Answer) In digital circuits glitch is an undesired transition that occurs before the signal settles to its intended value. In other words, glitch is an electrical pulse of short duration that is usually the result of a fault or design error. As shown in the adjacent diagram, there is some delay at the output O1, which results in a glitch at output O2. As there is some capacitance associated with the output O2, it leads to switching power dissipation. This switching power dissipation arising out of a glitch is known as glitching power dissipation. ( The inverter delay implies the delay taken by gate to reflect the output after change in inputs.)
These “extra” transitions can be minimized by
- Balancing all signal paths
- Reducing logic depth
Realization of A.B.C.D in cascaded form where there is possibility of glitch.
Balanced realization of the same function with lesser possibility of glitch
Q.4) Which is better - sign-magnitude form of number representation or 2’s complement form in terms of power dissipation?
Answer) In most of the signal processing applications, 2’s complement is typically chosen to represent numbers. Sign extension causes MSB sign-bits to switch when a signal transitions from positive to negative or vice versa; 2’s complement can result in significant switching activity when the signals being processed switch frequently around zero. Switching in MSBs can be minimized by using sign-magnitude representation.
Q.5) Why low power has become an important issue in the present day VLSI circuit realization?
Answer) In deep sub-micron technology the power has become as one of the most important issue because of :
- Increasing transistor count; the number of transistors is getting doubled in every 18 months based on Moore,s Law.
- Higher speed of operation; the power dissipation is proportional to the clock frequency.
- Greater device leakage currents; In nanometer technology the leakage component becomes a significant percentage of the total power and the leakage current increases at a faster rate than dynamic power in technology generations
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