Q.1) A task can have arguments of type :
A. Input only.
B. Output only.
C. Both input and output.
D. All input, output and inout.
Answer) D
Q.2) How many flops will be synthesized by the given code?
always @(posedge clk)
begin
Q1 <= d;
Q2 <= q1;
Q3 <= q2;
end
A. 1
B. 2
C. 3
D. None of the above.
Answer) C
Q.3) Which operator has the highest precedence in Verilog :
A. UnaryB. Multiplication
C. Addition
D. Conditional
Answer) A
Q.4) In the given code snippet, statement 2 will be executed at
initial
begin
#5 x = 1'b0; //statement 1
#15 y = 1'b1; //statement 2
end
A. 15B. 20
C. 5
D. Current simulation time.
Answer) B
Q.5) Variable and signal which will be updated first?
A. Variable
B. Signal
C. Can't say
D. None of the above.
(Registers represent variables used to store data.)
Answer) C
No comments:
Post a Comment