Q.1) Calculate the setup slack for the below example :
tclk-q =
300ps ; tsetup = 100ps ; tcombo = 400ps ; tclk
= 1000ps
Answer)
From the above waveform, we can derive the following equation :
tclk
= tclk-q + tcombo + tsetup + setup-slack
So, setup-slack = tclk – tclk-q – tcombo - tsetup
Hence, setup-slack = 1000 – 300 – 400 -200
= 100ps
Q.2) Calculate the minimum clock cycle time, for the above example.
Answer) For the minimum clock cycle time, the setup slack is zero.Hence, tclk = tclk-q + tcombo + tsetup + setup-slack becomes,
tclk (min.) = tclk-q + tcombo + tsetup
tclk (min.) = 300 + 400 + 200
tclk (min.) = 900ps
Q.3) Calculate the hold slack for the above example. (thold = 100ps)
Answer)
From the above waveform, the equation for the hold slack comes as :
hold-slack = tclk-q + tcombo – thold
hold-slack = tclk-q + tcombo – thold
hold-slack = 300 + 400 – 100
= 600ps
Q.4) Explain the worst case hold time scenario.
Answer) The following equation is an analysis of worst case hold time scenarios. In this case, two FFs are directly connected to each other, i.e. there is no combo delay.
As depicted in the diagram, output Q0 of FF0 is directly connected to D1 of FF1.
Since, for worst case : tcombo = 0So the equation becomes,
hold-slack = tclk-q – thold
Since, hold-slack > 0 , as to avoid hold violation.
tclk-q – thold > 0
tclk-q > thold
hold-slack = tclk-q + tcombo – thold
For Verilog timing tasks related to setup and timing checks, please go through this link.
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