Clock Skew

Clock skew

The operation of most digital circuit systems, such as computer systems, is synchronized by a "clock" that dictates the sequence and pacing of the devices on the circuit. Ideally, the input to each element has reached its final value before the next clock movement occurs so that the behaviour of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.

In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. Clock skew can be positive or negative. If the clock signals are in complete synchronicity, then the clock skew observed at the registers is zero.

Reasons for clock skew:

This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

Two types of skews are defined: Local skew and Global skew.

Local skew

Local skew is the difference in the arrival of clock signal at the clock pin of related flops.

Global skew

Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This is also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

Why clock skew is a problem?

Two types of violation can be caused by clock skew. One problem is caused when the clock travels slower than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through.

Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, because the new data was not set up and stable before the next clock tick arrived. 

A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Positive Skew

When the source flop is clocked first than the destination flop, the clock skew is called as positive skew.

From the below waveform, we can see that the hold slack reduces, when there is a positive skew. Hence, we can infer that the positive skew increases the chances of hold violation.

Negative Skew
When the destination is clocked before the source, the clock skew is called as negative skew.

From the waveform below, we can see that the setup slack decreases in case of negative skew. So, the negative skew increases the chances of setup violation.

Uncertainty
Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.

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