Synthesis Interview Questions - v1.0

Synthesis is the stage in the design flow which is concerned with translating the HDL code into gates - and that's putting it very simply! First of all, the HDL code must be written in a particular way for the synthesis tool that you are using to infer required hardware. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

Q.1)What value is inferred when multiple procedural assignments are made to the same reg variable in an always block?

Answer) When there are multiple non-blocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis. For example 

always @ (posedge clk) 

begin

     q <= a^b;

     q <= a & b;                                        

     q <= a|b;

end

                                         

Q.2) List out some synthesizable and non-synthesizable constructs.

Answer) 

Synthesizable	Non-Synthesizable
Assign	Initial block
For loop	Delay statements
Gate level primitives	Events
Repeat with constant value	Real data types
	Time data type
	Fork, Join

Q.3) What is the hardware that is inferred by the conditional operator?

Answer) Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals get inferred into a multiplexor. For example, the following is the code for a simple multiplexor.

assign y = (s == 1'b1) ? a1 : a0; 

    

Q.4) What logic is inferred when there are multiple assign statements targeting the same wire?

Answer) It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source. However, it is legal to drive a three-state wire by multiple assign statements

Q.5) Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?

Answer) Slow the clock down on the one with setup violations, as by slowing the clock the data will reach before the setup time window and will not violate the setup time. 

For removing hold violations, add redundant logic in the path where there are hold violations, as it will slow down the data path, and the data will not change in the hold window, thereby avoiding hold violation.