Edge Sensitive Paths, Conditional Path Delay and specparam statements

Edge-Sensitive Paths 

An edge-sensitive path construct is used to model the timing of input to output delays, which occurs only when a specified edge occurs at the signal.

Parallel Connection:
([edge_identifier] input_terminal => output_terminal [polarity]:data_source) = delays;

Full Connection :
([edge_identifier] input_terminal *> output_terminal [polarity]:data_source) = delays;

Edge identifier : posedge, negedge

Polarity : '+',  '-'

For more about parallel and full connection, please go through this post.

Example :

(posedge clock => (q +: d)) = (10 : 8)

At a positive edge on a 'clock' signal the value of 'q' will change, using the rising delay of 10 and the falling delay of 8 time unit. The data path travels from 'd' to 'q' and data 'd' is not inverted.

Rising : 0 -> 1, x -> 1, z -> 1
Falling : 1 -> 0, x -> 0, z -> 0
Turn off : 0 -> z, 1 -> z, x -> z

Conditional path delays

Sometimes, the pin-to-pin delay might change on the basis of the states of input signals to a circuit. Verilog allows path delays to be assigned conditionally, based on the value of the signals in the circuit. 

Conditional path delays are also known as state dependent path delays (SDPD).

Example :

<!-- language-all:  lang-verilog -->

module foo (out, a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

specify
//Parallel connection for different pin-to-pin timing on the basis of state of input signal
if (a)
(a => out) = 9;
if (~a)
(a => out) = 10;

//Full connection for different pin-to-pin timing on the basis of state of input signal
if ({c,d}) == 2'b01)
(c,d *> out) = 11;
else
(c,d *> out) = 13;
endspecify

and a1 (e, a, b);
and a2 (f, c, d);
and a3 (out, e, f);
endmodule

specparam statements

Special parameters can be declared for use inside a specify block. These parameters are declared by the keyword specparam. The specparam values can only be used inside their specify block and not elsewhere. The specify parameters are helpful while assigning delays as these values only need to be changed in case of new timing parameters, instead of changing the hardcoded values for each connection.

Example :
specify
specparam d_to_q = 8;
specparam clk_to_q = 10;

(d => q) = d_to_q;
(clk => q) = clk_to_q;
endspecify