Blocking, Nonblocking Assignments and Verilog Race Condition

Blocking Assignment

The blocking assignment operator is denoted by an equal sign ("="). The blocking assignment evaluates the RHS arguments and complete its assignment without interrupt from any other Verilog statement.

Execution of blocking assignments can be seen as a one-step process:

1. Evaluate the RHS and update the LHS of the blocking assignment without interruption from any other Verilog statement.

The problem occurs, when the RHS side of one assignment in one procedural block is same as the LHS side of another assignment in another procedural block and both the assignments are scheduled to be executed in the same simulation time step, then in this case there is no sure way to predict which assignment will occur first. This condition is known as Verilog race condition.  The race condition is shown using the below example

module tp ( output reg o1,
                  output reg o2,
                  input         clk,
                  input         rst
                );

    always @(posedge clk or posedge rst)
        if (rst) 
              o1 = 1; 
        else 
              o1 = o2; //------> I

    always @(posedge clk or posedge rst)
        if (rst) 
              o2 = 0; 
        else
              o2 = o1;  //-------> II
endmodule

In this case, when the design gets out of reset, we cannot predict whether statement I will be executed first or statement II. If statement I is executed first, then values of o1 = 0, o2 = 0 ; if statement II is executed first, then o1 = 1; o2 = 1, hence this is a Verilog race condition.

Nonblocking Assignment

The nonblocking assignment operator is denoted by "<=".  A nonblocking assignment evaluates the RHS side of a nonblocking statement at the beginning of a time step and schedules the LHS update to take place at the end of the time step. Between evaluation of the RHS expression and update of the LHS expression, other Verilog statements can be evaluated and updated and the RHS expression of other Verilog nonblocking assignments can also be evaluated and LHS updates scheduled.

Execution of nonblocking assignments can be seen as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step.
2. Update the LHS of nonblocking statements at the end of the time step.

module tp ( output reg o1,
                  output reg o2,
                  input         clk,
                  input         rst
                );

    always @(posedge clk or posedge rst)
        if (rst) 
              o1 <= 1; 
        else 
              o1 <= o2; //------> I

    always @(posedge clk or posedge rst)
        if (rst) 
              o2 <= 0; 
        else
              o2 <= o1;  //-------> II
endmodule

In this case, when reset is applied, o1 = '1' and o2 = '0', when the reset is de-asserted, the RHS side of both the statements are updated at the start of time step, but the assignment takes place only at the end of the time step, hence there is no race condition. At the end of time step , o1 = '0' and o2 = '1'.

S-R latch and flip-flop

Q.1) Explain S-R Latch using NAND gates.

Answer) Latch is a sequential logic circuit which checks all its inputs continuously and will change its output as soon as the input changes without waiting for the clock signal. Generally an enable signal is provided for a latch. When the enable signal is active, the output will change as soon as there is change in input.

It has two outputs Q and not(Q) which are complements of each other.

The boolean equation for the outputs can be expressed as follows :

           Q = not(R.not(Q))

     not(Q) = not(S.Q)

I) S = 0, R = 0 (Race Condition)

    Substituting the value of S and R in the above equations, we get both Q and not(Q) as 1. This is an indeterminate state and should be avoided.

II) S = 0, R = 1 (Reset Condition)

     Since, S = 0, it forces not(Q) to be 1 and R = 1 forces Q  = 0.

III) S = 1, R = 0 (Set Condition)

       In this case, R = 0 forces the Q = 1 and S = 1 forces not(Q) = 0.

IV) S = 1, R = 1 (No change)

       Substituting the values of S and R in the above equation, we get,

       Q = Q and not(Q) = not(Q), hence there is no change in the outputs.

Q.2) Explain positive edge triggered S-R flip flop.

Answer) The S-R flip flop consists of a differentiator circuit and a S-R gated latch. C-R₁ acts  as a differentiator and converts the rectangular clock pulses into positive and negative spikes. The diode acts as a rectifying diode and allows only the positive spikes to pass through, blocking the negative spikes.

Q.3) Draw the excitation table for S-R flip flop.

Answer) From the above truth table, we can infer following points :

• When Q retains state '0',  we have two conditions S = R = '0' and S = '0'; R = '1', hence to retain state '1',     S = '0' and R = 'x'
• When Q changes from 0' to '1', S = '1' ; R = '0'
• When Q  changes from '1' to '0', S = '0' ; R = '1'.
• When Q retains state '1' , we have two conditions S = R = '0' and S = '1'; R = '0', hence to retain state '1' ,     S='x' and R = '0'.

Q.4) Explain race condition.

Answer) Race condition occurs when both S and R input of latch becomes '0'. When any one input to a NAND gate is '0',  its output becomes '1'. Thus both the outputs will try to become '1', hence it is called race condition.