VLSI QnA

Verilog provides system tasks to do timing checks. There are many timing check system tasks available in Verilog. We will discuss the timin...

Edge-Sensitive Paths   An edge-sensitive path construct is used to model the timing of input to output delays, which occurs only when a s...

Specify Blocks : As we discussed in our last post , a delay between a source (input or inout) pin and a destination (output or inout) p...

Why delays are required in Verilog simulation? Functional verification of hardware only tells whether the functionality of design is corr...

Q.1) Explain metastability. Answer) A flip flop enters into meta-stable state, when the hold or setup window is violated. At this time, ...