Digital Design Interview Questions - v1.3

Q.1) Explain metastability.

Answer) A flip flop enters into meta-stable state, when the hold or setup window is violated. At this time, the output of flip flop is unpredictable.

If you want to read more about setup and hold violations, go through this post.

Q.2) What are the probable ways to avoid metastability?

Answer) Ways to avoid metastability :

1. Lowering clock frequency - Gives setup slack
2. Lowering data speed - Gives hold slack.
3. Faster flip flop - The setup and hold values are very less, hence chances for violation decreases.

Q.3) In a system with 

(a) Insufficient hold time , will slowing the clock frequency will help?

Answer) No, it doesn't help. Making the data path slower will help with hold time ,but could violate setup time.

(b) Insufficient setup time ,will slowing the clock frequency will help?

Answer) Yes, making data path faster will help setup time, but will violate in hold time.

Q.4) Design a clock divider circuit which divides the clock by an odd number and has 50% duty cycle. (o/p clk = i/p clk/N, where N is an odd number).

Answer) We will first examine an example where the input clock is divided by 3. After, which we will generalize the steps for any odd number.

Step I :

Design a odd number counter (in this case, counter which counts up-to 2)

2-bit counter

Truth table for divide by 3 counter

D0 = q1

D1 = not(q1).not(q0)

From the above simplifications, we can draw the circuit for divide by 3 counter.

Circuit for divide by 3 counter.

Divide by 3 counter waveform

Step II : 50% duty cycle 

Now, we have divided the input clock by 3, but the duty cycle is still not 50%. To get 50% duty cycle, we shift the Q0 output by 90 degrees and add a gate to OR the two flip flops' output.

Divide by 3 with 50% duty cycle

Please note that in above figure, the last flop has negated clock at its clock input terminal.

Divide by 3 with 50% duty cycle waveform

The above method can be extended to other odd larger by divide "N" numbers by following the same design flow :

1. Design a Up or Down divide by "N" counter.
2. Add a flip flop to follow one of the flip flops in the counter 1/2 clock cycle.
3. OR the output of added flip flop with the one that is driving it to achieve 50% duty cycle.