Verilog Timing Checks

Verilog provides system tasks to do timing checks. There are many timing check system tasks available in Verilog. We will discuss the timing check system tasks one by one. All timing checks must be inside the specify block only. Before starting with the timing check system tasks, let us first see the description of all arguments 

Timing check system tasks arguments

Please go through the the posts on setup and hold timing for better understanding of these tasks.

$setup

Checks setup time violation. 

Syntax : $setup(data_event, reference_event, limit[, notifier]);

Violation is reported if,   (T_{reference_event} – T_{data_event}) < limit

Example :$setup(data, posedge clock, 3);

$hold

Checks hold time violation.
Syntax : $hold(reference_event, data_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) < limit
Example :$hold(posedge clear, data, 5);

$width

Check that the width of a pulse meets the minimum width requirement.
Syntax : $width(reference_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) < limit
The data_event is explicitly specified for this system task. The data_event is the next opposite edge of the reference_event signal.
Example :$width(posedge clock, 6);

$recovery

Usually it is applied for checking reset recovery violation.
Syntax : $recovery(reference_event, data_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) < limit
Example :$recovery(posedge clock, reset, 5);

$skew

Used to check synchronicity of clocks inside a circuit.
Syntax : $skew(reference_event, data_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) > limit
Example : $skew(posedge clock1, posedge clock2, 5);

$setuphold

Checks setup and hold timing violations. It is a combination of $setup and $hold system tasks.
Syntax : $setuphold(reference_event, data_event, setup_limit, hold_limit[, notifier]);
Violation is reported if,    (T_{data_event} – T_{reference_event}) < hold_limit
                                      (T_{reference_event} – T_{data_event}) < setup_limit
Example :$setuphold(posedge clock, data, 5, 10);