Specify Block

Specify Blocks :

As we discussed in our last post, a delay between a source (input or inout) pin and a destination (output or inout) pin of a module is called a module path delay. Path delays are assigned in Verilog within the keywords specify and endspecify.  A specify block constitutes all the statements between the keyword specify and endspecify.

Placement of Specify Block :

A specify block is a separate block in the module, which neither comes under initial or always block.

Inside Specify Blocks :

Parallel connection

Usage : ( <source_field> => <destination_field>) = <delay_value>);

Examples :

//bit-to-bit connection. both i and out are single-bit. i is the 'source field' and out is the 'destination field'.

(i => out) = 6;

//vector connection. both i and out are 4-bit vectors.

(i => out) = 6;

The above statement can be expanded as follows :

(i[0] => out[0]) = 6;
(i[1] => out[1]) = 6;
(i[2] => out[2]) = 6;
(i[3] => out[3]) = 6;

//illegal connection i[4:0] is a 5-bit vector, out[3:0] is a 4-bit. Gives error; mismatch between bit width of source and destination fields.

Full connection

Usage : ( <source_field> *> <destination field>) = <delay_value>);

In a full connection, each bit in the source field connects to every bit in the destination field. The full connection overcomes the limitation of parallel connection in which the widths of source and destination field need to be same. The main use of the full connection is in in-fact, specifying delays between different source and destination fields' width.

Examples :

//i[31:0] is a 32-bit vector and out[15:0] is a 16-bit vector

//Delay of 6 between each bit of i and every bit of out is given as

specify
    (i *> out) = 6;
endspecify
//The expression would require 352 (16*32) parallel connections to specify the delays.

In our coming post , we will have a look at conditional path delays, specparam statements and how do you model edge sensitive delays.