VLSI Glossary

VLSI Glossary

ASIC	Application Specific Integrated Circuit
ATPG	Automatic Test Pattern Generation
AOCV	Advance On Chip Variation
BC	Best Case
CCS	Composite Current Source
CG	Composite Grain
CMP	Chemical Mechanical Planarization
CTS	Clock Tree Synthesis
CAD	Computer Aided Design
DDC	Synopsys Database Format (Synopsys specific)
DEF	Design Exchange Format
DFM	Design For Manufacture
DRC	Design Rule Check
DFT	Design For Test
DSPF	Detailed Standard Parasitic Format
ECO	Engineering Change Order
EM	Electro magnetic
ESD	Electro-Static Discharge
EDA	Electronic Design automation
EDIF	Electronic Design Interchange Format
FPGA	Field Programmable Gate Array
GDSII	Graphic Data System II
HVT	High Vt
HDLs	Hardware Descriptive language
IMD	Inter-Metal Dielectric
ILD	Inter Layer Dielectric
IO	Input Output
ITF	Interconnect Technology File
IC	Integrated Circuit
LEF	Library Exchange Format
LIB	Library
LVS	Layout Vs Schematic
LSI	Large Scale Integration
MCMM	Multi-Corner Multi-Mode
NDR	Non default Rule
NLDM	Non-Linear Delay models
OPC	Optical Proximity Correction
PG pin	Power and Ground Pin
PLIB	Physical Library
PLL	Phase Lock Loop
PVT	Process Voltage Temperature
PDEF	Physical Design Exchange Format
QOR	Quality Of Result
RAM	Random Access memory
ROM	Read Only Memory
RDL	Re-Distribution layer
RTL	Register Transfer Level
RSPF	Reduced Standard Parasitic Format
SAIF	Switching Activity Interchange Format
SDF	Standard Delay Format
SOC	System On Chip
SOI	Silicon On Insulator
SPEF	Standard Parasitic Exchange Format.
SPICE	Simulation Program for Integrated Circuits Emphasis
SSI	Small Scale Integration
SPF	Standard Parasitic Format
SBPF	Synopsys Binary Parasitic Format
SDC	Synopsys Design Constraint
TLF	Timing Library Format
TTL	Transistor-Transistor Logic
TF	Technology File
UPF	Unified Power Format
ULSI	Ultra Large Scale Integration
VCD	Value Change Dump
VHDL	VHSIC(Very High Speed Integrated Circuit) Hardware Descriptive Language
VLSI	Very large Scale Integration