Synthesis Interview Questions - v1.0

Synthesis is the stage in the design flow which is concerned with translating the HDL code into gates - and that's putting it very simply! First of all, the HDL code must be written in a particular way for the synthesis tool that you are using to infer required hardware. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

Q.1)What value is inferred when multiple procedural assignments are made to the same reg variable in an always block?

Answer) When there are multiple non-blocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis. For example 

always @ (posedge clk) 

begin

     q <= a^b;

     q <= a & b;                                        

     q <= a|b;

end

                                         

Q.2) List out some synthesizable and non-synthesizable constructs.

Answer) 

Synthesizable	Non-Synthesizable
Assign	Initial block
For loop	Delay statements
Gate level primitives	Events
Repeat with constant value	Real data types
	Time data type
	Fork, Join

Q.3) What is the hardware that is inferred by the conditional operator?

Answer) Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals get inferred into a multiplexor. For example, the following is the code for a simple multiplexor.

assign y = (s == 1'b1) ? a1 : a0; 

    

Q.4) What logic is inferred when there are multiple assign statements targeting the same wire?

Answer) It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source. However, it is legal to drive a three-state wire by multiple assign statements

Q.5) Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?

Answer) Slow the clock down on the one with setup violations, as by slowing the clock the data will reach before the setup time window and will not violate the setup time. 

For removing hold violations, add redundant logic in the path where there are hold violations, as it will slow down the data path, and the data will not change in the hold window, thereby avoiding hold violation.

CMOS Interview Questions - v1.0

 Q.1) What do you understand by UPF?

Answer) Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard was based on a donation from the Accellera organization.

UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process — RTL (register transfer level) or earlier.

UPF provides a consistent format to specify power-aware design information that cannot be specified in HDL code or when it is undesirable to directly specify within the HDL logic, as doing so would tie the logic specification directly to a constrained power implementation.

Q.2) Explain different approaches of state retention.

Answer) Given a power switching fabric and an isolation strategy, it is possible to power gate a block of logic, but unless a retention strategy is employed, all state information is lost when the block is powered down. To resume its operation on power up, the block must either have its state restored from an external source or build up its state from the reset condition. In either case, the time and power required can be significant. The following three approaches can be used. 

• A software approach based on reading and writing registers. 
• A scan-based approach based on the re-use of scan chains to store state off chip. 
• A register-based approach that uses retention registers.

Q.3) Explain glitching power dissipation and ways to minimize it.

Answer) In digital circuits glitch is an undesired transition that occurs before the signal settles to its intended value. In other words, glitch is an electrical pulse of short duration that is usually the result of a fault or design error. As shown in the adjacent diagram, there is some delay at the output O₁, which results in a glitch at output O2. As there is some capacitance associated with the output O2, it leads to switching power dissipation. This switching power dissipation arising out of a glitch is known as glitching power dissipation. ( The inverter delay implies the delay taken by gate to reflect the output after change in inputs.)

                               

These “extra” transitions can be minimized by

• Balancing all signal paths 
• Reducing logic depth

        

Realization of A.B.C.D in cascaded form where there is  possibility of glitch. 

Balanced realization of the same function with lesser possibility of glitch

Q.4) Which is better - sign-magnitude form of number representation or 2’s complement form in terms of power dissipation? 

Answer) In most of the signal processing applications, 2’s complement is typically chosen to represent numbers. Sign extension causes MSB sign-bits to switch when a signal transitions from positive to negative or vice versa; 2’s complement can result in significant switching activity when the signals being processed switch frequently around zero. Switching in MSBs can be minimized by using sign-magnitude representation.

Q.5) Why low power has become an important issue in the present day VLSI circuit realization? 

Answer) In deep sub-micron technology the power has become as one of the most important issue because of :

• Increasing transistor count; the number of transistors is getting doubled in every 18 months based on Moore,s Law. 
• Higher speed of operation; the power dissipation is proportional to the clock frequency. 
• Greater device leakage currents; In nanometer technology the leakage component becomes a significant percentage of the total power and the leakage current increases at a faster rate than dynamic power in technology generations

Clock Jitter

Jitter

Jitter is the short-term variations of a signal with respect to its ideal position in time. Jitter is the variation of the clock period from edge to edge. 

Clock jitter refers to temporal variation of clock period at a given point-that is, the clock period can reduce or expand on cycle by cycle basis. it is strictly a temporal uncertainty measure and is often specified at a given point on the chip. 

From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. Jitter can also be generated from PLL known as PLL jitter. Possible jitter values should be considered for proper PLL design. 

Jitter can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform

Sources of Jitter Common sources of jitter include:

• Internal circuitry of the phase-locked loop (PLL)
• Random thermal noise from a crystal
• Other resonating devices
• Random mechanical noise from crystal vibration
• Signal transmitters
• Traces and cables
• Connectors
• Receivers

Impact of Jitter on sequential system

Jitter directly impacts the performance of a sequential system. Ideally, the clock period starts at edge 2 and ends at edge 5 and with a nominal clock period of TCLK. However as a result of jitter, the worst case scenario happens when the leading edge of the current clock period is delayed (edge 3), and the leading edge of the next clock period occurs early (edge 4). As a result, the total time available to complete the operation is reduced by twice t_{jitter in the worst case.}

Clock Skew

Clock skew

The operation of most digital circuit systems, such as computer systems, is synchronized by a "clock" that dictates the sequence and pacing of the devices on the circuit. Ideally, the input to each element has reached its final value before the next clock movement occurs so that the behaviour of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.

In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. Clock skew can be positive or negative. If the clock signals are in complete synchronicity, then the clock skew observed at the registers is zero.

Reasons for clock skew:

This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

Two types of skews are defined: Local skew and Global skew.

Local skew

Local skew is the difference in the arrival of clock signal at the clock pin of related flops.

Global skew

Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This is also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

Why clock skew is a problem?

Two types of violation can be caused by clock skew. One problem is caused when the clock travels slower than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through.

Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, because the new data was not set up and stable before the next clock tick arrived. 

A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Positive Skew

When the source flop is clocked first than the destination flop, the clock skew is called as positive skew.

From the below waveform, we can see that the hold slack reduces, when there is a positive skew. Hence, we can infer that the positive skew increases the chances of hold violation.

Negative Skew
When the destination is clocked before the source, the clock skew is called as negative skew.

From the waveform below, we can see that the setup slack decreases in case of negative skew. So, the negative skew increases the chances of setup violation.

Uncertainty
Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.

ALSO READ : Clock Jiiter

Setup and Hold time for flip flops - Part 2

This post is in continuation to our previous post on Setup and Hold time for flip flops.

Q.1) Calculate the setup slack for the below example :

         t_clk-q = 300ps ; t_setup = 100ps ; t_combo = 400ps ; t_clk = 1000ps

Answer) 

                From the above waveform, we can derive the following equation :

                  t_clk = t_clk-q + t_combo + t_setup + setup-slack

                  So, setup-slack = t_clk – t_clk-q – t_combo  - t_setup

                  Hence, setup-slack = 1000 – 300 – 400 -200

                                          = 100ps

Q.2) Calculate the minimum clock cycle time, for the above example.

Answer) For the minimum clock cycle time, the setup slack is zero.
              Hence,  t_clk = t_clk-q + t_combo + t_setup + setup-slack becomes,
                      t_{clk (min.)} = t_clk-q + t_combo + t_setup
                      t_{clk (min.)} = 300 + 400 + 200
                      t_{clk (min.)} = 900ps 

Q.3) Calculate the hold slack for the above example. (t_hold = 100ps)

Answer) 

                From the above waveform, the equation for the hold slack comes as :
                                    hold-slack = t_clk-q + t_combo – t_hold

                             hold-slack = 300 + 400 – 100

                                          = 600ps

Q.4) Explain the  worst case hold time scenario.

Answer) The following equation is an analysis of worst case hold time scenarios. In this case, two FFs are directly connected to each other, i.e. there is no combo delay.

As depicted in the diagram, output Q0 of FF0 is directly connected to D1 of FF1.

Since, for worst case :  t_combo = 0
So the equation becomes,

                                    hold-slack = t_clk-q – t_hold

Since, hold-slack > 0 , as to avoid hold violation.

                                    t_clk-q – t_hold > 0

                                    t_clk-q > t_hold

                             hold-slack = t_clk-q + t_combo – t_hold       

For Verilog timing tasks related to setup and timing checks,  please go through this link.

Verilog Interview Questions - v1.2

Q.1) Explain $display, $monitor and $strobe?

Answer) All these commands have the same syntax.
$display :- The $display displays once the value of parameters, when it is executed.
$strobe :- The $strobe displays the parameter at the very end of the current simulation time.
$monitor :- The $monitor displays once every time one of it's parameters changes.

The format string is same as that of C/C++.
Format characters include :
Decimal              :- %d
Hexadecimal      :- %h
Binary                :- %b
Character           :- %c
String                 :- %s
Time                   :- %t
Hierarchy Level  :- %m

Syntax :-
$display("format_string", val1,  val2,....)
$strobe("format_string", val1, val2, ...)
$monitor("format_string", val1, val2,.....)

Q.2) What is the difference between:
         y = (sel)? i1 : i2;       and                if(sel) y = i1;
                                                                  else    y = i2;

Answer) The ternary operator "?" , merges the answer.
              Example : sel = 2'bx1; i1 = 2'b00; i0 = 2'b10;
                              y = 2'bx0;

               The "if" treats "X" or "Z" as false values, so the answer always be in false condition, i.e. i2.

Q.3) What is the difference between equality operator (==) and case equality operator(===)?

Answer) The equality operator (==) can give the output 0,1 or X.
               Case equality operator (===) only gives the output TRUE (1) or FALSE (0).
               If I1 = 3'bx01 ; I2 = 3'b1x0;
               I1 == I2 gives 'X';
               I1 === I2 gives '0';

Q.4) Explain the difference between task and function.

Answer)

Q.5) Write a verilog code to swap contents of two registers with and without a temporary register.

Answer) With temporary register :

               always@(posedge clock)

                begin

                    temp = b;

                    b = a;

                    a = temp;

                end

                Without temporary register :

                 always @(posedge clock)

                 begin

                    a <= b;

                    b <= a;

                 end

Setup and Hold time for flip flops

The most frequently asked question in the interview is regarding the timing of flops. Generally the questions asked are based on calculation of minimum time cycle (max. frequency), setup slack and hold slack. 

Consider a D –type edge-triggered, Flip Flop (FF). The time just before and just after the clock edge, is the critical time, where the D input must not change.

Region just before the clock is setup time (t_setup).

Region after the clock edge is hold time (t_hold).

Every flip flop has minimum required values for t_setup and t_hold. The values of t_setup and t_hold vary strongly with temperature, voltage and process.

What happens to Q if D input changes within the t_setup and t_hold window?

• Q may follow D correctly.
• Q may follow D incorrectly.
• Q may assume a metastable state for an indeterminate time followed by a transition to logic 1 or logic 0.

For correct operation, D inputs must be stable for t_setup prior to clock and stay stable for a t_hold afterwards.

Minimum Cycle Time:

Time taken by data to travel from one flop to another flop. Path between two flops is composed of :

• Clock to Q delay (t_clk-q).
• Propogation delay through the combo logic. (tcombo).
• The required setup time (t_setup) of FF1.

  

        t_min  = t_clk-q + t_combo + t_setup 

f_max = 1/t_min

Setup Slack:

The setup time is a function of the clock period, combo delay and the clk-to-output delay.

Actual t_setup = t_clk – t_clk-q - t_combo

As said earlier, each flop has a minimum specified t_setup.

The difference between the actual setup time and the minimum required setup time is known as setup slack.

Setup Slack = Actual t_setup – Reqd. t_setup

A positive slack is always desirable. 

For maximum frequency, the setup slack is zero.

Hold Time:

Hold time is the amount of time that FF0’s old data must persist at the D input of FF1, i.e. D1 after the clock edge.

Actual hold time = t_clk-q + t_combo.

Each flop has a minimum specified t_hold. The difference between the actual hold time and the minimum required hold time is known as hold slack.

Hold slack = Actual hold time – Reqd. t_hold 

For examples, please visit Setup and Hold time for flip flops - Part 2
For Verilog timing tasks related to setup and timing checks,  please go through this link.

Verilog Interview Questions - v1.1

Q.1) A task can have arguments of type :

         A. Input only.
          B. Output only.
          C. Both input and output.
          D. All input, output and inout.

          Answer) D

Q.2) How many flops will be synthesized by the given code?
        always @(posedge clk)
        begin
            Q1 <= d;
            Q2 <= q1;
            Q3 <= q2;
        end

       A. 1
         B. 2
         C. 3
         D. None of the above.

         Answer) C

  Q.3) Which operator has the highest precedence in Verilog :

         A. Unary
           B. Multiplication
           C. Addition
           D. Conditional

           Answer) A

Q.4) In the given code snippet, statement 2 will be executed at

         initial

         begin

            #5 x = 1'b0;        //statement 1

            #15 y = 1'b1;      //statement 2

         end

         A. 15
           B. 20
           C. 5
           D. Current simulation time.

           Answer) B

Q.5) Variable and signal which will be updated first?

       A. Variable
        B. Signal
        C. Can't say
        D. None of the above.

(Registers represent variables used to store data.)

        Answer) C

Digital Design Interview Questions - v1.2

Q.1) Design a combinational logic circuit which doubles the frequency of input clock. (Output clk freq. = 2*  input clk freq.) (Frequency multiplier(*2)).

Answer) To solve these kind of questions, first draw waveforms of given input and output clocks and then try to add one or more waveforms to input which when applied to a combinational gate  will give the output 

Consider the time period of input clock is T. If the input clock is delayed by T/4 time period and if this delayed clock along with original input clock is given to a combinational gate then one would see that only XOR gate fits in, to produce output with double the frequency of input clock.

Q.2) What kind of circuit is this :                                                            A and B are inputs to an AND gate. AND gate's output goes to one input of OR gate. The other input of OR gate comes from an EX-OR gate. Inputs to the Ex-OR gate are C and the output of the OR gate. 

         A) Combinatorial /Sequential?

         B)  Synchronous / Asynchronous?

Answer) Combinatorial and Asynchronous

Q.3) What is the function of a D FF whose complemented output ( Qbar ) is connected to its input,D. What is the maximum clock frequency that can be used for it?

Answer) Suppose that there was some value at the output Q('0') of the flip flop, so when rising edge of clock comes, it samples the inverted value of output and retains it until next clock. When next rising edge comes, flop samples inverted value of output and so on. This behaviour of circuit shows that output will be half of the clock.

The circuit behaves as a frequency divider(/2).

Q.4) To convert a 2-input NAND gate into inverter.

Answer) Two ways to convert a 2-input NAND gate into inverter :-

               a) Short both inputs of NAND gate

               b) Tie one of the inputs to ‘1’.

Q.5) If A ? B = C and A?C = B, then what is the operator "?"

Answer) Starting with OR gate,

               A or B = C ; A or C = B

               Replacing value of B in first equation,

               A or (A or C) =C ----> This is false, hence OR is not the answer.

                AND gate,

                A and B = C; A and C = B

                Replacing value of B in first equation,

                A and   (A and C) = C ---> This is again false, hence AND is not the answer.

                XOR gate,

                A xor B = C; A xor C = B

                Replacing value of B in first equation,

                A xor (A xor C) = C,

                A xor (A.not(C) + C.not(A)) = C,

                A.not(A.not(C) + C.not(A)) + not(A).(A.not(C) + C.not(A)) = C,

                A(not(A).not(C) + A.C) + not(A).C = C,

                0 + A.C + not(A).C = C,

                C = C, -----> This is true, hence XOR is the answer

                  

                These type of questions are usually solved using hit and trial method.

                

Digital Design Interview Questions - v1.1

Q.1) Implement OR and NOR using 2-to-1 multiplexer.

Answer) OR gate:
               Multiplexer equation: Y = I1.(S) + I0.not(S)
                                 I1 => '1' ; I0 => 'B' ; S => 'A'
                                                Y = 1.(A) + B.not(A)      
              Upon simplifying above equation, Y = A + B
               

                                               

                 











                NOR gate:
                Multiplexer equation: Y = I1.(S) + I0.not(S)
                                 I1 => '0' ; I0 => 'not(B)' ; S => 'A'
                                                Y = 0.(A) + not(B).not(A)      
                Upon simplifying above equation, Y = not(A+B)

                                           

Q.2) Implement EX-OR and EX-NOR gates using 2-to-1 multiplexer.

Answer) EX-OR gate:

               Multiplexer equation: Y = I1.(S) + I0.not(S)
                                 I1 => 'not(B)' ; I0 => 'B' ; S => 'A'
                                                Y = not(B).(A) + B.not(A)  
    

                                         
               

               EX-NOR gate:

               Multiplexer equation: Y = I1.(S) + I0.not(S)
                                 I1 => 'B' ; I0 => 'not(B)' ; S => 'A'
                                                Y = B.(A) + not(B).not(A)  

                                        

Q.3) Implement latch using 2-to-1 multiplexer.

Answer) Multiplexer equation: Y = I1.(S) + I0.not(S)

                                 I1 => 'D' ; I0 => 'Q' ; S => 'En'
                                                Y = D.(En) + Q.not(En)

Q.4) Implement D flip-flop using 2-to-1 multiplexer.

Answer) In the below implementation of flip flop, two muxes are used. The flip flop shown below is a negedge D flip flop.

Q.5) Implement T flip-flip using 2-to-1 multiplexer.

Answer) T flip-flop using D flip-flop :

Verilog Interview Questions - v1.0

Q.1) Verilog HDL originated at

      A.     AT&T Bell Laboratories

            B.     Defence Advanced Research Projects Agency (DARPA)

            C.     Gateway Design Automation

            D.     Institute of Electrical and Electronics Engineers (IEEE)

            Answer: C

Q.2) Verilog is an IEEE standard

1. IEEE 1346
2. IEEE 1364
3. IEEE 1394
4. IEEE 1349

    Answer: B  

Q.3) Which level of abstraction level is available in Verilog but not in VHDL?

1. Behavioral level
2. Dataflow level
3. Gate level
4. Switch level

    Answer: D

Q.4)  In Verilog  `h1234 is a

1. 16 bit hexadecimal number
2. 32 bit hexadecimal number
3. 4 bit hexadecimal number
4. It is invalid notation

    Answer: B

Q.5) Which logic level is not supported by Verilog?

1. U
2. X
3. Z
4. None of the above

    Answer: A

Digital Design Interview Questions - v1.0

Q.1) Implement inverter using NAND Gate?

Answer)  The key to solving such type of questions is, first draw the truth table of the gate given and then the table for what you want to achieve.
           
             

Truth table for AND and INVERTER Gate

                  From the truth table,

                         when both inputs => 0, output => 1 (same as inverter)

                         when both inputs => 1, output => 0 (same as inverter)

                 

                   Implementation of Inverter using NAND Gate.

Inverter using NAND gate

                    Another Implementation :

Inverter using NAND gate

                     NAND Expression : Y = not(A) or not (B)

                     If B => 1

                     Y = not(A) or not(1) => Y = not (A) or '0'

                                                           Y = not (A) ----> inverter

Q.2) Implement inverter using only NOR gate.

Answer)  NOR Expression: Y = not(A) and not(B)

                When both inputs => '0' , output => '1'

                When both inputs => '1' , output => '0'

                Another Implementation:

                NOR Expression : Y = not(A) and not(B)

                If B => '0'

                Y = not(A) and not(0)

                Y = not(A) and '1'

                Y = not(A) ---> inverter

Inverter using NOR gate

                           

Q.3) Implement inverter using 2-to-1 multiplexer.

Answer) Multiplexer Equation :
               Out = S1.S + S0.not(S)
                If S1 => '0' ; S0 => '1'
                Out = 0.(S) + 1.not(S),
                Out=  not(S) ---> inverter

Inverter using multiplexer

Q.4) Implement AND gate using 2-to-1 multiplexer.               

Answer) Multiplexer Equation :                     
               Out = S1.S + S0.not(S)
                If S0 => '0'
                Out = S1.S
                   S1 => 'A'
                Out = A.S    ---> AND gate

AND gate using multiplexer

Q.5) Implement NAND gate using 2-to-1 multiplexer.

Answer) Multiplexer Equation :
               Out = S1.S + S0.not (S)
               S0 => '1';
               S1 => not(A);
               Out = not(A).S + not(S)   ---> NAND gate
               Simplifying it further,
               Out = (not(S) + S)(not(A) + not(S))
               Out = 1.(not(A) + not(S))
               Out = not(A) + not(S)   ----> NAND gate
             

NAND gate using multiplexer