VLSI QnA: Synchronous and Asynchronous resets

Reset

Reset is needed for:

Forcing the digital circuit into a sane state for simulation
Initializing hardware, as circuits have no way to initialize themselves.
For simulation purpose, it is advantageous to have reset applied to all elements that have states.

Synchronous Resets :

Based on the fact that the reset will be sampled on the active edge of the clock. Reset is treated as any other input to the state machine.

Synchronous Resets

Advantages :

As there is no reset pin in the flop, the size is smaller.
The circuit becomes completely synchronous.
It provides filtering for the reset line so that it is not affected by glitches, unless they occur right at clock edge.

Disadvantages :

Since the reset input is added to combinatorial logic, hence the combinatorial logic becomes complex.
May require a pulse stretch circuit to guarantee that a reset pulse is wide enough to be seen at the rising clock edge.
Reset buffer tree may be required to ensure that all resets occur in the same clock cycle.
Require a free running clock to ensure reset takes place.

Asynchronous Resets :

Based on the fact that the reset has priority over other signals, when asserted, reset occurs. The main problem when dealing with the asynchronous resets is their removal; the asynchronous resets need to be de-asserted synchronously.

Asynchronous Resets

Advantages :

No clock is required for assertion of reset.
Data path is clear of reset signals.

Disadvantages :

The flop becomes sensitive to the glitches or noise present in the reset line.
The deactivation of reset of all flip flops must be synchronous.

Asynchronous Reset Problem

Problems with asynchronous de-assertion of asynchronous reset :

Violation of reset recovery time
Reset removal happening in different clock cycles for different sequential elements.

Reset Recovery Time :

Reset recovery time refers to the time between when reset is de-asserted and the time that the clock signal goes high again. Missing a recovery time can cause signal integrity or metastability problems with the registered data outputs.

Reset removal traversing different clock cycles :

When reset removal is asynchronous to the rising clock edge, slight differences in propagation delays in either or both the reset signal and the clock signal can cause some registers or flip-flops to exit the reset state before others.

Reset Synchronizer

Without a reset synchronizer, the usefulness of the asynchronous reset in the final system is void even if the reset works during simulation.

Reset Synchronizer

An external reset signal asynchronously resets a pair of master reset flip-flops, which then drives the master reset signal asynchronously through the reset buffer tree to the rest of the flip flops in the design. The entire design will be asynchronously reset.

Reset removal is done by de-asserting the reset signal, which in turn allows the d-input of the first master reset flip flop to pass through the reset synchronizer. The reason for using two flip flops is to remove any metastability that might be caused by the reset signal being removed asynchronously and too close to the rising clock edge. As two flip flops are used , it typically takes two active clock edges after reset removal to synchronize removal of master reset.

Timing Parameters related to Asynchronous Reset :

Recovery time is the minimum amount of time required between the release of an asynchronous signal from the active state to the next active clock edge.

Removal time specifies the minimum amount of time between an active clock edge and the release of an asynchronous control signal.