Google+ VLSI QnA: Verilog Interview Questions - v1.4

Tuesday, 6 May 2014

Verilog Interview Questions - v1.4

Q.1) If a net has no driver, it gets the value
        A) 0
        B) X
        C) Z
        D) U 

Answer) C

Q.2) What is the default value of reg?
         A) 0
         B) X
         C) Z
         D) U

Answer) B

Q.3) The task $stop is provided to
        A) End simulation
        B) Suspend simulation
        C) Exit simulator
        D) None of the above

Answer) B

Q.4) If A= 4`1xxz and B= 4`b1xxx, then A= = =B will return
        A) 1
        B) X
        C) Z
        D) 0

Answer) D

Q.5) Externally, a output port must always connected to a
        A) net only
        B) a reg only
        C) either net or reg
        D) None of the above

Answer) A

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