CMOS Interview Questions - v1.1

Q.1) Explain the difference between PMOS and NMOS.

Answer) A NMOS transistor is made up of n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows forming an n-type channel between the source and the drain and a current is carried by electrons from source to the drain through an induced n-type channel.

A PMOS transistor is made up of p-type source and drain and a n-type substrate. When a positive voltage is applied between the source and the gate (negative voltage between gate and source), a p-type channel is formed between the source and the drain with opposite polarities. A current is carried by holes from source to the drain through an induced p-type channel.

n-channel MOSFETs have some performance advantages over p-channel MOSFET’s. The mobility of electrons, which are carriers in the case of an n-channel device, is about two times greater than that of holes, which are the carriers in the p-channel device. Thus an n-channel device is faster than a p-channel device.

Advantages of PMOS :

• PMOS technology is highly controllable.
• It is a low cost process.
• It has good yield and high noise immunity.

Advantages of NMOS :

• Since electron mobility is twice (say) that of hole mobility, an n-channel device will have one-half the on-resistance or impedance of an equivalent p-channel device with the same geometry and under the same operating conditions. Thus n-channel transistors need only halt the size of p-channel devices to achieve the same impedance. Therefore, n-channel ICs can be smaller for the same complexity or, even more important, they can be more complex with no increase in silicon area.

• NMOS circuits offer a speed advantage over PMOS due to smaller junction areas. Since the operating speed of an MOS IC is largely limited by internal RC time constants and capacitance of diode is directly proportional to its size, an n-channel junction can have smaller capacitance. This, in turn, improves its speed.

Disadvantages of NMOS :

• The n-channel device has following problems in the device processing. Most of the mobile contaminants are positively charged. Since NMOS operates with the gate positively based with respect to the substrate, these ions collect along the oxide-silicon interface. This charge causes a shift in VTh. Also, there is fixed positive charge at the Si-SiO2 interface resulting from various steps of the manufacturing process. This also shifts the threshold voltage. Both these charges have tendency to make the device normally on. These two charges exist in PMOS device too, but the positive ions are pulled to the AI-S1O2 interlace by the negative bias applied to gate. There, they cannot affect the device threshold severely.

• Another problem with NMOS device occurs during the oxidation of silicon which takes place at the Si-SiO2 interface. No real abrupt change occurs between silicon and Si02; rather there is a transition zone. This transition zone contains positively charged Silicon atoms which increase the absolute magnitude of the threshold voltage for a p-channel device and decrease the absolute magnitude of the threshold voltage for an n-channel device. This means it is difficult to make an n-channel device that is off at zero gate voltage. This is why it is more difficult to make an n-channel device than a p-channel device.

Q.2) Draw the CMOS layout of NAND gate.

Answer) NAND gate equation : output = not(A.B)

                                                  output = not(A) + not(B)

              The CMOS layout consists of PMOS and NMOS. For drawing PMOS layout use the given equation. For NMOS take the complement of the equation and draw it. 

+ -> in parallel.

.  -> in series.

So, the PMOS equation comes as :

      PMOS equation : not(A) + not(B)

and the NMOS equation as follows :

      NMOS equation : A.B

Q.3) Draw the CMOS layout of NOR gate.

Answer) NOR gate equation : output = not(A+B)

                                                output = not(A).not(B)

PMOS  equation : not(A).not(B)

NMOS equation : A + B

Q.4) Why are NAND gates preferred over NOR gates?

Answer) NAND gate is better gate for design than NOR because at the transistor level, the mobility of electrons is higher than the mobility of holes. Inorder to make the rise and fall times of a gates equal usually the width of PMOS transistor is made higher, so the resistance of it would be less and can attain equal rise and fall times.

In NAND gates the PMOS transistors are connected in parallel and there by its effective resistance decreases. So now one can achieve the same rise and fall times at lower widths of the PMOS, whereas in NOR gate, the PMOS transistors are connected in series, thereby increasing the resistance and also the rise time.

Q.5) Draw the CMOS, PMOS and NMOS layout of inverter.

Answer) NOT gate equation : output = not(A)

  

PMOS equation : not(A)

NMOS equation : A