Blocking, Nonblocking Assignments and Verilog Race Condition

Blocking Assignment

The blocking assignment operator is denoted by an equal sign ("="). The blocking assignment evaluates the RHS arguments and complete its assignment without interrupt from any other Verilog statement.

Execution of blocking assignments can be seen as a one-step process:

1. Evaluate the RHS and update the LHS of the blocking assignment without interruption from any other Verilog statement.

The problem occurs, when the RHS side of one assignment in one procedural block is same as the LHS side of another assignment in another procedural block and both the assignments are scheduled to be executed in the same simulation time step, then in this case there is no sure way to predict which assignment will occur first. This condition is known as Verilog race condition.  The race condition is shown using the below example

module tp ( output reg o1,
                  output reg o2,
                  input         clk,
                  input         rst
                );

    always @(posedge clk or posedge rst)
        if (rst) 
              o1 = 1; 
        else 
              o1 = o2; //------> I

    always @(posedge clk or posedge rst)
        if (rst) 
              o2 = 0; 
        else
              o2 = o1;  //-------> II
endmodule

In this case, when the design gets out of reset, we cannot predict whether statement I will be executed first or statement II. If statement I is executed first, then values of o1 = 0, o2 = 0 ; if statement II is executed first, then o1 = 1; o2 = 1, hence this is a Verilog race condition.

Nonblocking Assignment

The nonblocking assignment operator is denoted by "<=".  A nonblocking assignment evaluates the RHS side of a nonblocking statement at the beginning of a time step and schedules the LHS update to take place at the end of the time step. Between evaluation of the RHS expression and update of the LHS expression, other Verilog statements can be evaluated and updated and the RHS expression of other Verilog nonblocking assignments can also be evaluated and LHS updates scheduled.

Execution of nonblocking assignments can be seen as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step.
2. Update the LHS of nonblocking statements at the end of the time step.

module tp ( output reg o1,
                  output reg o2,
                  input         clk,
                  input         rst
                );

    always @(posedge clk or posedge rst)
        if (rst) 
              o1 <= 1; 
        else 
              o1 <= o2; //------> I

    always @(posedge clk or posedge rst)
        if (rst) 
              o2 <= 0; 
        else
              o2 <= o1;  //-------> II
endmodule

In this case, when reset is applied, o1 = '1' and o2 = '0', when the reset is de-asserted, the RHS side of both the statements are updated at the start of time step, but the assignment takes place only at the end of the time step, hence there is no race condition. At the end of time step , o1 = '0' and o2 = '1'.

Synthesis Interview Questions - v1.0

Synthesis is the stage in the design flow which is concerned with translating the HDL code into gates - and that's putting it very simply! First of all, the HDL code must be written in a particular way for the synthesis tool that you are using to infer required hardware. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.

Q.1)What value is inferred when multiple procedural assignments are made to the same reg variable in an always block?

Answer) When there are multiple non-blocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis. For example 

always @ (posedge clk) 

begin

     q <= a^b;

     q <= a & b;                                        

     q <= a|b;

end

                                         

Q.2) List out some synthesizable and non-synthesizable constructs.

Answer) 

Synthesizable	Non-Synthesizable
Assign	Initial block
For loop	Delay statements
Gate level primitives	Events
Repeat with constant value	Real data types
	Time data type
	Fork, Join

Q.3) What is the hardware that is inferred by the conditional operator?

Answer) Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals get inferred into a multiplexor. For example, the following is the code for a simple multiplexor.

assign y = (s == 1'b1) ? a1 : a0; 

    

Q.4) What logic is inferred when there are multiple assign statements targeting the same wire?

Answer) It is illegal to specify multiple assign statements to the same wire in a synthesizable code that will become an output port of the module. The synthesis tools give a syntax error that a net is being driven by more than one source. However, it is legal to drive a three-state wire by multiple assign statements

Q.5) Given two ASICs. one has setup violation and the other has hold violation. how can they be made to work together without modifying the design?

Answer) Slow the clock down on the one with setup violations, as by slowing the clock the data will reach before the setup time window and will not violate the setup time. 

For removing hold violations, add redundant logic in the path where there are hold violations, as it will slow down the data path, and the data will not change in the hold window, thereby avoiding hold violation.

Verilog Interview Questions - v1.2

Q.1) Explain $display, $monitor and $strobe?

Answer) All these commands have the same syntax.
$display :- The $display displays once the value of parameters, when it is executed.
$strobe :- The $strobe displays the parameter at the very end of the current simulation time.
$monitor :- The $monitor displays once every time one of it's parameters changes.

The format string is same as that of C/C++.
Format characters include :
Decimal              :- %d
Hexadecimal      :- %h
Binary                :- %b
Character           :- %c
String                 :- %s
Time                   :- %t
Hierarchy Level  :- %m

Syntax :-
$display("format_string", val1,  val2,....)
$strobe("format_string", val1, val2, ...)
$monitor("format_string", val1, val2,.....)

Q.2) What is the difference between:
         y = (sel)? i1 : i2;       and                if(sel) y = i1;
                                                                  else    y = i2;

Answer) The ternary operator "?" , merges the answer.
              Example : sel = 2'bx1; i1 = 2'b00; i0 = 2'b10;
                              y = 2'bx0;

               The "if" treats "X" or "Z" as false values, so the answer always be in false condition, i.e. i2.

Q.3) What is the difference between equality operator (==) and case equality operator(===)?

Answer) The equality operator (==) can give the output 0,1 or X.
               Case equality operator (===) only gives the output TRUE (1) or FALSE (0).
               If I1 = 3'bx01 ; I2 = 3'b1x0;
               I1 == I2 gives 'X';
               I1 === I2 gives '0';

Q.4) Explain the difference between task and function.

Answer)

Q.5) Write a verilog code to swap contents of two registers with and without a temporary register.

Answer) With temporary register :

               always@(posedge clock)

                begin

                    temp = b;

                    b = a;

                    a = temp;

                end

                Without temporary register :

                 always @(posedge clock)

                 begin

                    a <= b;

                    b <= a;

                 end

Verilog Interview Questions - v1.1

Q.1) A task can have arguments of type :

         A. Input only.
          B. Output only.
          C. Both input and output.
          D. All input, output and inout.

          Answer) D

Q.2) How many flops will be synthesized by the given code?
        always @(posedge clk)
        begin
            Q1 <= d;
            Q2 <= q1;
            Q3 <= q2;
        end

       A. 1
         B. 2
         C. 3
         D. None of the above.

         Answer) C

  Q.3) Which operator has the highest precedence in Verilog :

         A. Unary
           B. Multiplication
           C. Addition
           D. Conditional

           Answer) A

Q.4) In the given code snippet, statement 2 will be executed at

         initial

         begin

            #5 x = 1'b0;        //statement 1

            #15 y = 1'b1;      //statement 2

         end

         A. 15
           B. 20
           C. 5
           D. Current simulation time.

           Answer) B

Q.5) Variable and signal which will be updated first?

       A. Variable
        B. Signal
        C. Can't say
        D. None of the above.

(Registers represent variables used to store data.)

        Answer) C