VLSI QnA

This blog provides VLSI interview questions.

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Tuesday, 20 May 2014

Blocking, Nonblocking Assignments and Verilog Race Condition

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Blocking Assignment The blocking assignment operator is denoted by an equal sign ("="). The blocking assignment evaluates the R...
Monday, 19 May 2014

Finite State Machine (FSM)

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Ways to design clocked sequential circuits :  Mealy Machine  Moore Machine  Mealy Machine In a Mealy machine, the outputs are a func...
Sunday, 18 May 2014

Synchronous and Asynchronous resets

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Reset Reset is needed for: Forcing the digital circuit into a sane state for simulation Initializing hardware, as circuits have no wa...
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Saturday, 17 May 2014

T Flip Flop

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Q.1) Explain T flip flop. Answer) Toggle flip flop is basically a J_K flip flop with its inputs tied together. Analyzing the circuit, ...
Monday, 12 May 2014

Verilog Interview Questions - v1.5

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Q.1) If a pure combinational circuit is coded inside always block, is it necessary to mention all  of the inputs in the sensitivity list? ...
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