Q.1) If a pure combinational circuit is coded inside always block, is it necessary to mention all of the inputs in the sensitivity list?
Answer) Yes, in a pure combinational circuit it is advisable to mention all of the inputs in the sensitivity list, as not doing so may create different result in pre-synthesis and post-synthesis simulation, as during the synthesis, the tool considers all the input in the sensitivity list, whereas, simulation tool only considers the given inputs in the sensitivity list.
Q.2) If in1= 4'b011 and in2= 4'b0011, then the result of in1**in2 will be
A) 6
B) 9
C) 27
D) Invalid expression
Answer) C
Q.3) Give three methods to generate clock in Verilog.
Answer)
I) initial
begin
clk = 0;
end
always
begin
#(CLK_PERIOD/2) clk = ~clk;
end
II) initial
begin
clk = 0;
forever
begin
#(CLK_PERIOD/2) clk = ~clk;
end
end
III) initial
begin
clk = 0;
end
always
begin
#(CLK_PERIOD/2) clk = 0;
#(CLK_PERIOD/2) clk = 1;
end
Q.4) What will be the output of the following case statement?
wire [3:0] temp;
always @(...)
begin
case (1'b1)
temp[0] : Block 1;
temp[1] : Block 2;
temp[2] : Block 3;
temp[3] : Block 4;
endcase
end
Answer) The case statement walks down the list of options and executes the first one that matches. So, for example if, the MSB of temp is the only '1' in temp, then Block 4 statements will be executed.
Q.5) Why the statement "if (2'b10 & 2'b01)." doesn't behave as expected, i.e. return true case?
Answer) This is one of the most common coding error. In this case, the operator that is used is the bitwise AND(&) operator, whereas the correct operator that should have been used is the logical AND operator(&&).
For more Verilog Interview Questions, click here.
No comments:
Post a Comment