Google+ VLSI QnA: Task
Showing posts with label Task. Show all posts
Showing posts with label Task. Show all posts

Thursday, 24 April 2014

Verilog Interview Questions - v1.2

Q.1) Explain $display, $monitor and $strobe?

Answer) All these commands have the same syntax.
$display :- The $display displays once the value of parameters, when it is executed.
$strobe :- The $strobe displays the parameter at the very end of the current simulation time.
$monitor :- The $monitor displays once every time one of it's parameters changes.

The format string is same as that of C/C++.
Format characters include :
Decimal              :- %d
Hexadecimal      :- %h
Binary                :- %b
Character           :- %c
String                 :- %s
Time                   :- %t
Hierarchy Level  :- %m

Syntax :-
$display("format_string", val1,  val2,....)
$strobe("format_string", val1, val2, ...)
$monitor("format_string", val1, val2,.....)

Q.2) What is the difference between:
         y = (sel)? i1 : i2;       and                if(sel) y = i1;
                                                                  else    y = i2;

Answer) The ternary operator "?" , merges the answer.
              Example : sel = 2'bx1; i1 = 2'b00; i0 = 2'b10;
                              y = 2'bx0;

               The "if" treats "X" or "Z" as false values, so the answer always be in false condition, i.e. i2.

Q.3) What is the difference between equality operator (==) and case equality operator(===)?

Answer) The equality operator (==) can give the output 0,1 or X.
               Case equality operator (===) only gives the output TRUE (1) or FALSE (0).
               If I1 = 3'bx01 ; I2 = 3'b1x0;
               I1 == I2 gives 'X';
               I1 === I2 gives '0';

Q.4) Explain the difference between task and function.

Answer)
Difference between task and function

Q.5) Write a verilog code to swap contents of two registers with and without a temporary register.

Answer) With temporary register :
               always@(posedge clock)
                begin
                    temp = b;
                    b = a;
                    a = temp;
                end

                Without temporary register :
                 always @(posedge clock)
                 begin
                    a <= b;
                    b <= a;
                 end


Wednesday, 23 April 2014

Verilog Interview Questions - v1.1

Q.1) A task can have arguments of type :

         A. Input only.
          B. Output only.
          C. Both input and output.
          D. All input, output and inout.


          Answer) D

Q.2) How many flops will be synthesized by the given code?
        always @(posedge clk)
        begin
            Q1 <= d;
            Q2 <= q1;
            Q3 <= q2;
        end

       A. 1
         B. 2
         C. 3
         D. None of the above.


         Answer) C

  Q.3) Which operator has the highest precedence in Verilog :

         A. Unary
           B. Multiplication
           C. Addition
           D. Conditional

           Answer) A

Q.4) In the given code snippet, statement 2 will be executed at

         initial

         begin

            #5 x = 1'b0;        //statement 1

            #15 y = 1'b1;      //statement 2

         end

         A. 15
           B. 20
           C. 5
           D. Current simulation time.

           Answer) B

Q.5) Variable and signal which will be updated first?

       A. Variable
        B. Signal
        C. Can't say
        D. None of the above.


(Registers represent variables used to store data.)


        Answer) C