VLSI QnA

This post is continuation to our previous post on blocking and non-blocking assignments . For better understanding of how the blocking and ...

Verilog "Stratified Event Queue" The Verilog event queue is a conceptual model, which helps us understand how various events l...

Blocking Assignment The blocking assignment operator is denoted by an equal sign ("="). The blocking assignment evaluates the R...

Ways to design clocked sequential circuits :  Mealy Machine  Moore Machine  Mealy Machine In a Mealy machine, the outputs are a func...

Reset Reset is needed for: Forcing the digital circuit into a sane state for simulation Initializing hardware, as circuits have no wa...