Verilog Timing Checks

Verilog provides system tasks to do timing checks. There are many timing check system tasks available in Verilog. We will discuss the timing check system tasks one by one. All timing checks must be inside the specify block only. Before starting with the timing check system tasks, let us first see the description of all arguments 

Timing check system tasks arguments

Please go through the the posts on setup and hold timing for better understanding of these tasks.

$setup

Checks setup time violation. 

Syntax : $setup(data_event, reference_event, limit[, notifier]);

Violation is reported if,   (T_{reference_event} – T_{data_event}) < limit

Example :$setup(data, posedge clock, 3);

$hold

Checks hold time violation.
Syntax : $hold(reference_event, data_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) < limit
Example :$hold(posedge clear, data, 5);

$width

Check that the width of a pulse meets the minimum width requirement.
Syntax : $width(reference_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) < limit
The data_event is explicitly specified for this system task. The data_event is the next opposite edge of the reference_event signal.
Example :$width(posedge clock, 6);

$recovery

Usually it is applied for checking reset recovery violation.
Syntax : $recovery(reference_event, data_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) < limit
Example :$recovery(posedge clock, reset, 5);

$skew

Used to check synchronicity of clocks inside a circuit.
Syntax : $skew(reference_event, data_event, limit[, notifier]);
Violation is reported if,   (T_{data_event} – T_{reference_event}) > limit
Example : $skew(posedge clock1, posedge clock2, 5);

$setuphold

Checks setup and hold timing violations. It is a combination of $setup and $hold system tasks.
Syntax : $setuphold(reference_event, data_event, setup_limit, hold_limit[, notifier]);
Violation is reported if,    (T_{data_event} – T_{reference_event}) < hold_limit
                                      (T_{reference_event} – T_{data_event}) < setup_limit
Example :$setuphold(posedge clock, data, 5, 10);

Edge Sensitive Paths, Conditional Path Delay and specparam statements

Edge-Sensitive Paths 

An edge-sensitive path construct is used to model the timing of input to output delays, which occurs only when a specified edge occurs at the signal.

Parallel Connection:
([edge_identifier] input_terminal => output_terminal [polarity]:data_source) = delays;

Full Connection :
([edge_identifier] input_terminal *> output_terminal [polarity]:data_source) = delays;

Edge identifier : posedge, negedge

Polarity : '+',  '-'

For more about parallel and full connection, please go through this post.

Example :

(posedge clock => (q +: d)) = (10 : 8)

At a positive edge on a 'clock' signal the value of 'q' will change, using the rising delay of 10 and the falling delay of 8 time unit. The data path travels from 'd' to 'q' and data 'd' is not inverted.

Rising : 0 -> 1, x -> 1, z -> 1
Falling : 1 -> 0, x -> 0, z -> 0
Turn off : 0 -> z, 1 -> z, x -> z

Conditional path delays

Sometimes, the pin-to-pin delay might change on the basis of the states of input signals to a circuit. Verilog allows path delays to be assigned conditionally, based on the value of the signals in the circuit. 

Conditional path delays are also known as state dependent path delays (SDPD).

Example :

<!-- language-all:  lang-verilog -->

module foo (out, a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

specify
//Parallel connection for different pin-to-pin timing on the basis of state of input signal
if (a)
(a => out) = 9;
if (~a)
(a => out) = 10;

//Full connection for different pin-to-pin timing on the basis of state of input signal
if ({c,d}) == 2'b01)
(c,d *> out) = 11;
else
(c,d *> out) = 13;
endspecify

and a1 (e, a, b);
and a2 (f, c, d);
and a3 (out, e, f);
endmodule

specparam statements

Special parameters can be declared for use inside a specify block. These parameters are declared by the keyword specparam. The specparam values can only be used inside their specify block and not elsewhere. The specify parameters are helpful while assigning delays as these values only need to be changed in case of new timing parameters, instead of changing the hardcoded values for each connection.

Example :
specify
specparam d_to_q = 8;
specparam clk_to_q = 10;

(d => q) = d_to_q;
(clk => q) = clk_to_q;
endspecify

Specify Block

Specify Blocks :

As we discussed in our last post, a delay between a source (input or inout) pin and a destination (output or inout) pin of a module is called a module path delay. Path delays are assigned in Verilog within the keywords specify and endspecify.  A specify block constitutes all the statements between the keyword specify and endspecify.

Placement of Specify Block :

A specify block is a separate block in the module, which neither comes under initial or always block.

Inside Specify Blocks :

Parallel connection

Usage : ( <source_field> => <destination_field>) = <delay_value>);

Examples :

//bit-to-bit connection. both i and out are single-bit. i is the 'source field' and out is the 'destination field'.

(i => out) = 6;

//vector connection. both i and out are 4-bit vectors.

(i => out) = 6;

The above statement can be expanded as follows :

(i[0] => out[0]) = 6;
(i[1] => out[1]) = 6;
(i[2] => out[2]) = 6;
(i[3] => out[3]) = 6;

//illegal connection i[4:0] is a 5-bit vector, out[3:0] is a 4-bit. Gives error; mismatch between bit width of source and destination fields.

Full connection

Usage : ( <source_field> *> <destination field>) = <delay_value>);

In a full connection, each bit in the source field connects to every bit in the destination field. The full connection overcomes the limitation of parallel connection in which the widths of source and destination field need to be same. The main use of the full connection is in in-fact, specifying delays between different source and destination fields' width.

Examples :

//i[31:0] is a 32-bit vector and out[15:0] is a 16-bit vector

//Delay of 6 between each bit of i and every bit of out is given as

specify
    (i *> out) = 6;
endspecify
//The expression would require 352 (16*32) parallel connections to specify the delays.

In our coming post , we will have a look at conditional path delays, specparam statements and how do you model edge sensitive delays. 

Delay Models in Verilog

Why delays are required in Verilog simulation?

Functional verification of hardware only tells whether the functionality of design is correct or not. However, in real hardware, logic elements and path have delays associated with them. Therefore, it is also required that design meets timing requirements.

There are three types of delay models used in Verilog simulation - distributed, lumped and pin-to-pin (path) delays. We'll look into each delay model one by one.

Distributed Delay

Distributed delays are specified on a per element basis. Each individual logic element is assigned a specific delay value. In the two code examples below, it is shown that how delays are specified to individual gates (primitives) and assign statements.

Distributed Delay

Example 1: Distributed Delay applied to individual gates.
module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

//Delay is applied to each gate.
and #4 a1(e, a, b);
and #3 a2(f, c, d);
and #5 a3(out, e, f);
endmodule

Example 2: Distributed Delay applied using assign statement.
module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

//Delay is applied to each assign statement.
        assign #4 e = a & b;
        assign #3 f = c & d;
        assign #5 out = e & f;
endmodule

Lumped Delay

Lumped delays are specified on a per module basis. They are specified as a single delay on the output gate of the module. The lumped delay takes into consideration the maximum delay from an input to output. From the above, example we can see the maximum delay from input to output is 9 time units (delay from input a to output out), so this delay is mapped to the output gate of the module.

Lumped Delay

Example 3:Lumped Delay Model

module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

//Delay only applied to output gate.
and a1(e, a, b);
and a2(f, c, d);
and #9 a3(out, e, f);
endmodule

Pin-to-Pin Delays

In the pin-to-pin delay model, delays are assigned individually to paths from each input to output. Although pin-to-pin delays may look very detailed, but they are easier for designer, as it requires no knowledge of internals of module. The module may be coded in behavioral statements, data flow, gates, or mixed design. These delays are also known as path delays.

Pin-to-Pin Delay

For the above figure, pin-to-pin delay are specified as follows :

path a-e-out delay = 9

path b-e-out delay = 9

path c-f-out delay = 8

path d-f-out delay = 8

In our next post, we will see how the path delays are specified in Verilog.

Digital Design Interview Questions - v1.3

Q.1) Explain metastability.

Answer) A flip flop enters into meta-stable state, when the hold or setup window is violated. At this time, the output of flip flop is unpredictable.

If you want to read more about setup and hold violations, go through this post.

Q.2) What are the probable ways to avoid metastability?

Answer) Ways to avoid metastability :

1. Lowering clock frequency - Gives setup slack
2. Lowering data speed - Gives hold slack.
3. Faster flip flop - The setup and hold values are very less, hence chances for violation decreases.

Q.3) In a system with 

(a) Insufficient hold time , will slowing the clock frequency will help?

Answer) No, it doesn't help. Making the data path slower will help with hold time ,but could violate setup time.

(b) Insufficient setup time ,will slowing the clock frequency will help?

Answer) Yes, making data path faster will help setup time, but will violate in hold time.

Q.4) Design a clock divider circuit which divides the clock by an odd number and has 50% duty cycle. (o/p clk = i/p clk/N, where N is an odd number).

Answer) We will first examine an example where the input clock is divided by 3. After, which we will generalize the steps for any odd number.

Step I :

Design a odd number counter (in this case, counter which counts up-to 2)

2-bit counter

Truth table for divide by 3 counter

D0 = q1

D1 = not(q1).not(q0)

From the above simplifications, we can draw the circuit for divide by 3 counter.

Circuit for divide by 3 counter.

Divide by 3 counter waveform

Step II : 50% duty cycle 

Now, we have divided the input clock by 3, but the duty cycle is still not 50%. To get 50% duty cycle, we shift the Q0 output by 90 degrees and add a gate to OR the two flip flops' output.

Divide by 3 with 50% duty cycle

Please note that in above figure, the last flop has negated clock at its clock input terminal.

Divide by 3 with 50% duty cycle waveform

The above method can be extended to other odd larger by divide "N" numbers by following the same design flow :

1. Design a Up or Down divide by "N" counter.
2. Add a flip flop to follow one of the flip flops in the counter 1/2 clock cycle.
3. OR the output of added flip flop with the one that is driving it to achieve 50% duty cycle.