VLSI Glossary

VLSI Glossary

ASIC	Application Specific Integrated Circuit
ATPG	Automatic Test Pattern Generation
AOCV	Advance On Chip Variation
BC	Best Case
CCS	Composite Current Source
CG	Composite Grain
CMP	Chemical Mechanical Planarization
CTS	Clock Tree Synthesis
CAD	Computer Aided Design
DDC	Synopsys Database Format (Synopsys specific)
DEF	Design Exchange Format
DFM	Design For Manufacture
DRC	Design Rule Check
DFT	Design For Test
DSPF	Detailed Standard Parasitic Format
ECO	Engineering Change Order
EM	Electro magnetic
ESD	Electro-Static Discharge
EDA	Electronic Design automation
EDIF	Electronic Design Interchange Format
FPGA	Field Programmable Gate Array
GDSII	Graphic Data System II
HVT	High Vt
HDLs	Hardware Descriptive language
IMD	Inter-Metal Dielectric
ILD	Inter Layer Dielectric
IO	Input Output
ITF	Interconnect Technology File
IC	Integrated Circuit
LEF	Library Exchange Format
LIB	Library
LVS	Layout Vs Schematic
LSI	Large Scale Integration
MCMM	Multi-Corner Multi-Mode
NDR	Non default Rule
NLDM	Non-Linear Delay models
OPC	Optical Proximity Correction
PG pin	Power and Ground Pin
PLIB	Physical Library
PLL	Phase Lock Loop
PVT	Process Voltage Temperature
PDEF	Physical Design Exchange Format
QOR	Quality Of Result
RAM	Random Access memory
ROM	Read Only Memory
RDL	Re-Distribution layer
RTL	Register Transfer Level
RSPF	Reduced Standard Parasitic Format
SAIF	Switching Activity Interchange Format
SDF	Standard Delay Format
SOC	System On Chip
SOI	Silicon On Insulator
SPEF	Standard Parasitic Exchange Format.
SPICE	Simulation Program for Integrated Circuits Emphasis
SSI	Small Scale Integration
SPF	Standard Parasitic Format
SBPF	Synopsys Binary Parasitic Format
SDC	Synopsys Design Constraint
TLF	Timing Library Format
TTL	Transistor-Transistor Logic
TF	Technology File
UPF	Unified Power Format
ULSI	Ultra Large Scale Integration
VCD	Value Change Dump
VHDL	VHSIC(Very High Speed Integrated Circuit) Hardware Descriptive Language
VLSI	Very large Scale Integration

Interview Questions on Blocking and Nonblocking Assignments

This post is continuation to our previous post on blocking and non-blocking assignments. For better understanding of how the blocking and nonblocking assignments are scheduled in Verilog, please go through this post.

Q.1) What will be the output of following code?

         module seq;
         reg clk, rst, d;
         initial
         begin
               $monitor("%g clk = %b rst = %b d = %b", $time, clk, rst, d);
               #1   clk = 0;
               #10 rst = 0;
               #5   d = 0;
               #10 $finish;
          end
          endmodule

Answer) 0     clk = x   rst = x   d = x
              1     clk = 0   rst = x   d = x
              11   clk = 0   rst = 0   d = x
              16   clk = 0   rst = 0   d = 0

Q.2) What will be the output of following code?

         module parallel;
         reg clk, rst, d;
         initial
         begin
             $monitor("%g clk = %b rst = %b d = %b", $time, clk, rst, d);
             fork
                   #1   clk = 0;
                   #10  rst = 0;
                   #5   d = 0;
             join
             #1 display("%t Terminating simulation", $time);
         end
         endmodule
(Note : fork-join block causes the statements to be evaluated in parallel, i.e. all at the same time.)

Answer) 0     clk = x    rst = x   d = x

              1     clk = 0    rst = x   d = x

              5     clk = 0    rst = x   d = 0

             10    clk = 0    rst = 0   d = 0

             11    Terminating simulation

Q.3) What will be the output of the following code ?

         blocking                                                                          nonblocking

         always @(i1 or i2)                                                          always @(i1 or i2)

         begin                                                                               begin

                i1 = 1;                                                                              i1 = 1;

                i2 = 2;                                                                              i2 = 2;

                #10;                                                                                 #10;

                i1 = i2;                                                                             i1  <= i2;

                i2 = i1;                                                                             i2  <= i1;

         end                                                                                  end

                      (a)                                                                                   (b)

Answer) In the case of (a), i.e. blocking the values of i1 and i2 will be both '2', whereas in the case of (b) (nonblocking) the values of i1 and i2 will be '2' and '1' respectively.

    

Q.4) What will be the output of the following code ?

         module tp;
                reg i1;
                initial 

                      $monitor("\$monitor: i1 = %b", i1);
                initial 

                begin
                       $strobe ("\$strobe : i1 = %b", i1);
                       i1 = 0;
                       i1 <= 1;
                       $display ("\$display: i1 = %b", i1);
                      #1 $finish;

                end
         endmodule

Answer) $display: i1 = 0
              $monitor: i1 = 1
              $strobe : i1 = 1

Q.5) What will be the output of the following code?

         module tp;

                  reg i1, i2;

                  initial 

                  begin

                           i1 = 0;

                           i2 = 1;

                           i1 <= i2;

                           i2 <= i1;

                           $monitor ("%0dns: \$monitor: i1=%b i2=%b", $stime, i1, i2);

                           $display ("%0dns: \$display: i1=%b i2=%b", $stime, i1, i2);

                           $strobe ("%0dns: \$strobe : i1=%b i2=%b\n", $stime, i1, i2);

                    #0   $display ("%0dns: #0 : i1=%b i2=%b", $stime, i1, i2);

                    #1   $monitor ("%0dns: \$monitor: i1=%b i2=%b", $stime, i1, i2);

                           $display ("%0dns: \$display: i1=%b i2=%b", $stime, i1, i2);

                           $strobe ("%0dns: \$strobe : i1=%b i2=%b\n", $stime, i1, i2);

                           $display ("%0dns: #0 : i1=%b i2=%b", $stime, i1, i2);

                     #1  $finish;

                  end

         endmodule

Answer) 0ns: $display: i1=0 i2=1

              0ns: #0 : i1=0 i2=1

              0ns: $monitor: i1=1 i2=0

              0ns: $strobe : i1=1 i2=0

              1ns: $display: i1=1 i2=0

              1ns: #0 : i1=1 i2=0

              1ns: $monitor: i1=1 i2=0

              1ns: $strobe : i1=1 i2=0

In case of any doubt regarding the above solutions, feel free to leave a comment.

Verilog "Stratified Event Queue"

Verilog "Stratified Event Queue"

The Verilog event queue is a conceptual model, which helps us understand how various events like blocking assignments, nonblocking assignments function.

According to the Verilog IEEE standard, the Verilog event queue is logically segmented into five different regions.

1) Active Events :

     Events which occur at the current simulation time and can be executed in any order. These include blocking assignments, continuous assignments, $display commands, evaluation of instance and primitive inputs followed by updates of primitive and instance outputs, and the evaluation of nonblocking RHS expressions.

2) Inactive Events.

     Events which are processed after the processing of active events. In this queue, #0 delay assignments are scheduled.

3) Nonblocking assign update events

     Events that were evaluated during previous simulation time, but are assigned at this simulation time after the processing of active and inactive events. It is these queue where the LHS of nonblocking assignment is updated.

4) Monitor Events

    Events that are processed after all the active, inactive and nonblocking assign update events have been processed. This queue contains $monitor and $strobe assignments.

5) Future Events
     Events to occur at future simulation time.

Verilog Event Queue model

Example :
What will be the output of following piece of code?
initial
begin
     a = 1'b0;
     a <= 1'b1;
     $display("\nValue of a is :%b", a);
end
     
Many of us think that the the value of a displayed will be '1', but it is not correct. Using the Verilog event queue,
I) a = 1'b0;
   This will be placed in the active events, so the assignment will take place immediately. Hence, at this time , the value of a is '0'.

II) a <= 1'b1;
     As you remember from our previous post on nonblocking assignments, the nonblocking assignment is a two step process, so only RHS evaluation will be scheduled in active event. At this point the LHS will not be updated, so the value of a still remains '0'.

III) $display("\nValue of a is :%b",a);
      Since, it is a display statement the statement will be placed in active events and processed immediately, so we get the value of a printed as '0'.

IV) In this step, the LHS of nonblocking statement in II will be updated, at this time the value of a will change from '0' to '1'.