Blocking, Nonblocking Assignments and Verilog Race Condition

Blocking Assignment

The blocking assignment operator is denoted by an equal sign ("="). The blocking assignment evaluates the RHS arguments and complete its assignment without interrupt from any other Verilog statement.

Execution of blocking assignments can be seen as a one-step process:

1. Evaluate the RHS and update the LHS of the blocking assignment without interruption from any other Verilog statement.

The problem occurs, when the RHS side of one assignment in one procedural block is same as the LHS side of another assignment in another procedural block and both the assignments are scheduled to be executed in the same simulation time step, then in this case there is no sure way to predict which assignment will occur first. This condition is known as Verilog race condition.  The race condition is shown using the below example

module tp ( output reg o1,
                  output reg o2,
                  input         clk,
                  input         rst
                );

    always @(posedge clk or posedge rst)
        if (rst) 
              o1 = 1; 
        else 
              o1 = o2; //------> I

    always @(posedge clk or posedge rst)
        if (rst) 
              o2 = 0; 
        else
              o2 = o1;  //-------> II
endmodule

In this case, when the design gets out of reset, we cannot predict whether statement I will be executed first or statement II. If statement I is executed first, then values of o1 = 0, o2 = 0 ; if statement II is executed first, then o1 = 1; o2 = 1, hence this is a Verilog race condition.

Nonblocking Assignment

The nonblocking assignment operator is denoted by "<=".  A nonblocking assignment evaluates the RHS side of a nonblocking statement at the beginning of a time step and schedules the LHS update to take place at the end of the time step. Between evaluation of the RHS expression and update of the LHS expression, other Verilog statements can be evaluated and updated and the RHS expression of other Verilog nonblocking assignments can also be evaluated and LHS updates scheduled.

Execution of nonblocking assignments can be seen as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step.
2. Update the LHS of nonblocking statements at the end of the time step.

module tp ( output reg o1,
                  output reg o2,
                  input         clk,
                  input         rst
                );

    always @(posedge clk or posedge rst)
        if (rst) 
              o1 <= 1; 
        else 
              o1 <= o2; //------> I

    always @(posedge clk or posedge rst)
        if (rst) 
              o2 <= 0; 
        else
              o2 <= o1;  //-------> II
endmodule

In this case, when reset is applied, o1 = '1' and o2 = '0', when the reset is de-asserted, the RHS side of both the statements are updated at the start of time step, but the assignment takes place only at the end of the time step, hence there is no race condition. At the end of time step , o1 = '0' and o2 = '1'.

Finite State Machine (FSM)

Ways to design clocked sequential circuits : 

• Mealy Machine 
• Moore Machine 

Mealy Machine

In a Mealy machine, the outputs are a function of the present state and the value of inputs. Due to this, outputs may change asynchronously with change in inputs.

Output = f(Present State, Input)

Moore Machine

In a Moore machine, the outputs depend only on the present state. In the case of Moore Machine, the next state is calculated using the inputs and the current state. The outputs are computed by a combinatorial logic circuit whose inputs are the state variables.

Output = f(Present State)

Please go through the excitation table for D - flip flop for better understanding.

Q) Design a circuit that detects three consecutive '1's using Mealy and Moore FSM.

Answer)
I) Mealy FSM

Mealy FSM

State truth table

Y = In.q1

Q1 = In.q1 + In.q0

Q0 = In.not(q1).not(q0)

Mealy FSM circuit implementation

II) Moore FSM

Moore FSM

State truth table

Output truth table

Y = q0.q1

Q1 = In.q0 + In.q1

Q0 = In.q1 + In.not(q0)

Moore FSM circuit implementation

Synchronous and Asynchronous resets

Reset

Reset is needed for:

• Forcing the digital circuit into a sane state for simulation
• Initializing hardware, as circuits have no way to initialize themselves.
• For simulation purpose, it is advantageous to have reset applied to all elements that have states.

Synchronous Resets :

Based on the fact that the reset will be sampled on the active edge of the clock. Reset is treated as any other input to the state machine.

Synchronous Resets

Advantages :

• As there is no reset pin in the flop, the size is smaller.
• The circuit becomes completely synchronous.
• It provides filtering for the reset line so that it is not affected by glitches, unless they occur right at clock edge.

Disadvantages :

• Since the reset input is added to combinatorial logic, hence the combinatorial logic becomes complex.
• May require a pulse stretch circuit to guarantee that a reset pulse is wide enough to be seen at the rising clock edge.
• Reset buffer tree may be required to ensure that all resets occur in the same clock cycle.
• Require a free running clock to ensure reset takes place.

Asynchronous Resets :

Based on the fact that the reset has priority over other signals, when asserted, reset occurs. The main problem when dealing with the asynchronous resets is their removal; the asynchronous resets need to be de-asserted synchronously.

Asynchronous Resets

Advantages :

• No clock is required for assertion of reset.
• Data path is clear of reset signals.

Disadvantages :

• The flop becomes sensitive to the glitches or noise present in the reset line.
• The deactivation of reset of all flip flops must be synchronous.

Asynchronous Reset Problem

Problems with asynchronous de-assertion of asynchronous reset :

1. Violation of reset recovery time
2. Reset removal happening in different clock cycles for different sequential elements.

Reset Recovery Time :

Reset recovery time refers to the time between when reset is de-asserted and the time that the clock signal goes high again. Missing a recovery time can cause signal integrity or metastability problems with the registered data outputs.

Reset removal traversing different clock cycles :

When reset removal is asynchronous to the rising clock edge, slight differences in propagation delays in either or both the reset signal and the clock signal can cause some registers or flip-flops to exit the reset state before others.

Reset Synchronizer

Without a reset synchronizer, the usefulness of the asynchronous reset in the final system is void even if the reset works during simulation.

Reset Synchronizer

An external reset signal asynchronously resets a pair of master reset flip-flops, which then drives the master reset signal asynchronously through the reset buffer tree to the rest of the flip flops in the design. The entire design will be asynchronously reset.

Reset removal is done by de-asserting the reset signal, which in turn allows the d-input of the first master reset flip flop to pass through the reset synchronizer. The reason for using two flip flops is to remove any metastability that might be caused by the reset signal being removed asynchronously and too close to the rising clock edge. As two flip flops are used , it typically takes two active clock edges after reset removal to synchronize removal of master reset.

Timing Parameters related to Asynchronous Reset :

Recovery time is the minimum amount of time required between the release of an asynchronous signal from the active state to the next active clock edge.

Removal time specifies the minimum amount of time between an active clock edge and the release of an asynchronous control signal.

Reset Recovery time and Reset Removal time

T Flip Flop

Q.1) Explain T flip flop.

Answer) Toggle flip flop is basically a J_K flip flop with its inputs tied together.

Analyzing the circuit,
I) When CLK = ↓ , T = '0' / '1',
     There is no change in the output.

II) When CLK = '0' , T = '0' / '1',
     There is no change in the output.

III) When CLK = '1' , T = '0' / '1',
       There is no change in the output.

IV) When CLK = ↑ , T = '0',
       There is no change in the output ,as J = '0' and K = '0' .

READ : J-K Flip Flop

V)  When CLK = ↑ , T = '1',
      The output gets toggled, as J = '1' and K = '1'.

Truth table for T flip flop

Q.2) Draw the excitation table for T flip flop.

Answer) From the truth table, we can infer the following points.
              When Q retains its state either from '0' to '0' or '1' to '1', T = '0'
              When Q changes its state from '1' to '0' or '0' to '1', T ='1'.

Excitation table for T flip flop

Q.3) Convert J-K flip flip to T flip flop.

Answer) Given flop : J-K flip flop (Output)

               Flop to be derived : T flip flop (Input)

Combined truth table for converting J-K flip flop into T flip flop.

                                                            

K-Map Simplification

T flip flop using J-K flip flop

Q.4) Convert S-R flip flop into T flip-flop.

Answer) Given flip flop : S-R flip flop (Output)

               Flop to be derived : T flip flop (Input)

Combined truth table for converting S-R flip flop into T flip-flop

                                                                                    K-Map Simplification                    

T flip flop using S-R flip flop.

ALSO READ : S-R Flip Flop

Q.5) Convert D flip flop to T flip flop.

Answer) Given flop : D flip flop. (Output)

              Flop to be derived : T flip flop (Input)

Combined truth table for converting D flip into T flip flop

K-Map Simplification

T flip flop using D flip flop

Q.6) Convert T flip flop to D flip flop

Answer) Given flop : T flip flop

               Flop to be derived : D flip flop.

Combined truth table for converting T flip flop into D flip flop

K-Map Simplification

D flip flop using T flip flop.

READ : D Flip Flop

Q.7) Convert T flip flop to S-R flip flop.

Answer) Given flop : T flip flop (Output)

              Flop to be derived : S-R flip flop (Input)

Combined truth table for converting T flip flop into S-R flip flop.

K-Map Simplification

S-R flip flop using T flip-flop.

Q.8) Convert T flip flop into J-K flip flop.

Answer) Given flop : T flip flop (Output).

              Flop to be derived : J-K flip flop (Input)

Combined truth table for converting T flip flop into J-K flip flop.

K-Map Simplification

J-K flip flop using T flip flop.

Interesting Fact : Full form of JK in J-K flip flop is Jack Kilby.

Verilog Interview Questions - v1.5

Q.1) If a pure combinational circuit is coded inside always block, is it necessary to mention all  of the inputs in the sensitivity list? 

Answer) Yes, in a pure combinational circuit it is advisable to mention all of the inputs in the sensitivity list, as not doing so may create different result in pre-synthesis and post-synthesis simulation, as during the synthesis, the tool considers all the input in the sensitivity list, whereas, simulation tool only considers the given inputs in the sensitivity list.

Q.2) If in1= 4'b011 and in2= 4'b0011, then the result of in1**in2 will be

        A) 6
        B) 9
        C) 27
        D) Invalid expression

Answer) C

Q.3) Give three methods to generate clock in Verilog.

Answer)

I) initial 

   begin

      clk = 0;

   end

  

   always 

   begin

      #(CLK_PERIOD/2) clk = ~clk;

   end

II)   initial 

       begin

          clk = 0;

          forever 

          begin

              #(CLK_PERIOD/2) clk = ~clk;

          end

      end

III) initial 

      begin

          clk = 0;

      end

      always 

      begin

           #(CLK_PERIOD/2) clk = 0;

           #(CLK_PERIOD/2) clk = 1;

      end

Q.4) What will be the output of the following case statement?
        wire [3:0] temp;
        always @(...)
        begin
            case (1'b1)
                 temp[0] : Block 1;
                 temp[1] : Block 2;
                 temp[2] : Block 3;
                 temp[3] : Block 4;
            endcase
        end

Answer) The case statement walks down the list of options and executes the first one that matches. So, for example if, the MSB of temp is the only '1' in temp, then Block 4 statements will be executed. 

Q.5) Why the statement "if (2'b10 & 2'b01)." doesn't behave as expected, i.e. return true case? 

Answer) This is one of the most common coding error. In this case, the operator that is used is the bitwise AND(&) operator, whereas the correct operator that should have been used is the logical AND operator(&&).

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